The VIP4 is a highly configurable, RISC-based, intelligent interface processor. Up to two separate port adapters (PAs) can be configured on each VIP4. PAs provide the media-specific interfaces for the VIPs, enabling the VIP4 configuration to be optimized in terms of price, performance, and density. More than 50 media-specific LAN and WAN PAs are supported, including Fast Ethernet, T1/E1, High-Speed Serial Interface (HSSI), T3/E3, T3/E3 ATM, multichannel T1/E1, multichannel T3/E3, OC-3 ATM, packet over SONET (POS), and OC-12 ATM.
The VIP4 greatly increases the switching performance of the Cisco 7500 series and serves as an ideal platform for new, higher-speed, higher-density LAN and WAN interfaces. On the Cisco 7500 series, VIP4 distributed switching scales system performance to over two million packets per second (pps). In addition, the VIP4 features Single-Error-Correction, Double-Error-Detection Code (SECDED) logic, detecting and correcting single event upsets within a data word. This enables greater system resiliency and continued system availability in the presence of a single-event parity upset.
A key VIP4 feature is its ability to receive and execute on route information provided by the master Route Switch Processor (RSP). Based on this route data, a VIP4 can make its own Layer 3 switching decisions, providing a scalable, distributed switching architecture, called distributed switching (DSW). Further, DSW scales packet-processing throughput of a VIP4-equipped router, and resources for route policy and administration are increased by off-loading the central processor of packet-handling tasks.
The VIP4-80 is designed for the most demanding environments with increased processor performance and very large memory options. It offers 80 percent greater distributed switching performance over VIP4-50 from its 250-MHz MIPS RM7000 processor. In addition, the enhanced memory architecture of the VIP4 series provides substantially greater packet memory than previous VIPs. This feature supports environments with long round-trip propagation delays for wide-area network links and environments that use distributed IP services such as D-WRED and distributed committed access rate (D-CAR) queuing systems. Large program memory options enable support for switching methodologies such as CEF that eliminate performance bottlenecks caused by random destination addressing typically found in the Internet and large enterprise networks.